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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 general description the max15058 high-efficiency, current-mode, synchro - nous step-down switching regulator with integrated power switches delivers up to 3a of output current. the device operates from 2.7v to 5.5v and provides an output voltage from 0.6v up to 94% of the input voltage, making the device ideal for distributed power systems, portable devices, and preregulation applications. the max15058 utilizes a current-mode control archi - tecture with a high-gain transconductance error ampli - fier. the current-mode control architecture facilitates easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. the max15058 offers selectable skip-mode functional - ity to reduce current consumption and achieve a higher efficiency at light output load. the low r ds(on) inte - grated switches ensure high efficiency at heavy loads while minimizing critical inductances, making the layout design a much simpler task with respect to discrete solutions. utilizing a simple layout and footprint assures first-pass success in new designs. the max15058 features a 1mhz, factory-trimmed, fixed- frequency pwm mode operation. the high switching fre - quency, along with the pwm current-mode architecture, allows for a compact, all-ceramic capacitor design. the max15058 offers a capacitor-programmable soft- start reducing inrush current, startup into prebias operations, and a pgood open-drain output that can be used as an interrupt and for power sequencing. the max15058 is available in a 9-bump (3 x 3 array), 1.5mm x 1.5mm wlp package and is specified over the -40 n c to +85 n c temperature range. applications distributed power systems preregulators for linear regulators portable devices notebook power server power ip phones features s internal 30m i (typ) r ds(on) high-side and 18m i (typ) low-side mosfets at 5v s continuous 3a output current over temperature s 95% efficiency with 3.3v output at 3a s 1% output voltage accuracy over load, line, and temperature s operates from 2.7v to 5.5v supply s cycle-by-cycle overcurrent protection s adjustable output from 0.6v to up to 0.94 x v in s programmable soft-start s factory-trimmed, 1mhz switching frequency s stable with low-esr ceramic output capacitors s safe-startup into prebiased output s external reference input s skip-mode functionality s enable input/power-good output s fully protected against overcurrent and overtemperature s input undervoltage lockout 19-5478; rev 2; 7/11 + denotes a lead(pb)-free/rohs-compliant package. ordering information typical operating circuit evaluation kit available part temp range pin-package max15058ewl+ -40c to +85c 9 wlp in lx output 1.8v/3a input 2.8v to 5.5v gnd fb comp pgood en skip s s/ refin on off enable max15058
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 2 ______________________________________________________________________________________ electrical characteristics (v in = 5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) absolute maximum ratings note 1: lx has internal clamp diodes to gnd and in. applications that forward bias these diodes should not exceed the ics pack - age power dissipation limits. in, pgood to gnd ................................................ -0.3v to +6v lx to gnd .................................................. -0.3v to (v in + 0.3v) lx to gnd ....................................... -1v to (v in + 0.3v) for 50ns en, comp, fb, ss/refin, skip to gnd ... -0.3v to (v in + 0.3v) lx current (note 1) ................................................... -6a to +6a output short-circuit duration .................................... continuous continuous power dissipation (t a = +70 n c) 9-bump wlp multilayer board (derate 14.1mw/ n c above t a = +70 n c) .................... 1127mw operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -65 n c to +150 n c soldering temperature (reflow) ...................................... +260 n c wlp junction-to-case thermal resistance ( b jc ) ................... 26 n c/w junction-to-ambient thermal resistance ( b ja ) .............. 71 n c/w note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . package thermal characteristics (note 2) parameter symbol conditions min typ max units in voltage range v in 2.7 5.5 v in shutdown supply current v en = 0v 0.2 2 f a in supply current i in v en = 5v, v fb = 0.65v, no switching 1.56 2.3 ma v in undervoltage lockout threshold lx starts switching, v in rising 2.6 2.7 v v in undervoltage lockout hysteresis lx stops switching, v in falling 200 mv error amplifier transconductance g mv 1.5 ms voltage gain a vea 90 db fb set-point accuracy v fb over line, load, and temperature 594 600 606 mv fb input bias current i fb v fb = 0.6v -500 +500 na comp to current-sense transconductance g mc 18 a/v comp clamp low v fb = 0.65v, v ss = 0.6v 0.94 v power switches lx on-resistance, high-side pmos 30 m i lx on-resistance, low-side nmos 18 m i high-side switch current-limit threshold i hscl 5 a low-side switch sink current- limit threshold 4 a low-side switch source current- limit threshold 5 a
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = 5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) note 3: specifications are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design and characterization. parameter symbol conditions min typ max units lx leakage current v en = 0v 10 f a rms lx output current 3 a oscillator switching frequency f sw 850 1000 1150 khz maximum duty cycle d max 94 % minimum controllable on-time 70 ns slope compensation ramp valley 1.15 v slope compensation ramp amplitude v slope extrapolated to 100% duty cycle 320 mv enable en input high threshold voltage v en rising 1.45 v en input low threshold voltage v en falling 0.4 v en input leakage current v en = 5v 0.025 f a skip input leakage current v skip = v en = 5v 25 f a soft-start, prebias, refin soft-start current i ss v ss/refin = 0.45v, sourcing 10 f a ss/refin discharge resistance r ss i ss/refin = 10ma, sinking 8.3 i ss/refin prebias mode stop voltage v ss/refin rising 0.58 v external reference input range 0 in - 1.8 v hiccup number of consecutive current- limit events to hiccup 8 events timeout 1024 clock cycles power-good output pgood threshold v fb rising 0.535 0.555 0.575 v pgood threshold hysteresis v fb falling 28 mv pgood v ol i pgood = 5ma, v fb = 0.5v 20 60 mv pgood leakage v pgood = 5v, v fb = 0.65v 0.013 f a thermal shutdown thermal shutdown threshold 150 n c thermal shutdown hysteresis temperature falling 20 n c
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 4 ______________________________________________________________________________________ typical operating characteristics (v in = 5v, v out = 1.8v, i load = 3a, circuit of figure 5, t a = +25 n c, unless otherwise noted.) output voltage vs. output current max15058 toc07 output voltage (v) 1.89 1.87 1.85 1.83 1.81 1.79 1.77 1.75 output current (a) 0 0.5 1.0 2.0 1.5 2.5 3.0 v out = 5v v out = 3.3v output voltage vs. supply voltage max15058 toc06 output voltage (v) 1.89 1.87 1.85 1.83 1.81 1.79 1.77 1.75 supply voltage (v) 2.7 3.2 3.7 4.7 4.2 5.2 i out = 0.5a switching frequency vs. input voltage max15058 toc05 input voltage (v) switching frequency (khz) 920 940 960 980 1000 1020 1040 1060 1080 1100 900 2.7 3.2 3.7 4.7 4.2 5.2 efficiency vs. output current (skip mode) max15058 toc04 output current (a) efficiency (%) 2.5 2.0 1.5 1.0 0.5 80 85 90 95 100 75 0 3.0 v in = 3.3v v out = 1.8v v out = 1.5v v out = 1.2v v out = 2.5v efficiency vs. load current (skip mode) max15058 toc03 output current (a) efficiency (%) 2.5 2.0 1.5 1.0 0.5 80 85 90 95 100 70 75 0 3.0 v in = 5v v out = 1.8v v out = 1.5v v out = 1.2v v out = 2.5v v out = 3.3v efficiency vs. output current (forced pwm) max15058 toc02 output current (a) efficiency (%) 2.5 2.0 1.5 1.0 0.5 80 85 90 95 100 75 0 3.0 v in = 3.3v v out = 1.8v v out = 1.5v v out = 1.2v v out = 2.5v efficiency vs. load current (pwm mode) max15058 toc01 output current (a) efficiency (%) 2.5 2.0 1.5 1.0 0.5 80 85 90 95 100 75 0 3.0 v out = 3.3v v in = 5v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 _______________________________________________________________________________________ 5 typical operating characteristics (continued) (v in = 5v, v out = 1.8v, i load = 3a, circuit of figure 5, t a = +25 n c, unless otherwise noted.) shutdown waveform max15058 toc12 v out 1v/div v enable 5v/div v pgood 5v/div i lx 1a/div 10 s/div input and output waveforms (i out = 3a) max15058 toc11 input 20mv/div ac-coupled output 100mv/div ac-coupled 400ns /div switching waveform in skip mode (i out = 10ma) max15058 toc10 v out 50mv/div ac-coupled v lx 5v/div i lx 1a/div 10 s/div switching waveforms (i out = 3a) max15058 toc09b v out 20mv/div ac-coupled i lx 1av/div v lx 5v/div 0a v in = 3.3v 400ns /div switching waveforms (i out = 3a) max15058 toc09a v out 20mv/div ac-coupled i lx 1av/div v lx 5v/div 0a 400ns /div load-transient response max15058 toc08 50mv/div ac-coupled 1a/div 100s /div
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 6 ______________________________________________________________________________________ typical operating characteristics (continued) (v in = 5v, v out = 1.8v, i load = 3a, circuit of figure 5, t a = +25 n c, unless otherwise noted.) fb voltage vs. temperature max15058 toc17 ambient temperature ( c) feedback voltage (v) 80 60 40 20 0 -20 596 598 600 602 604 606 594 -40 no load rms input current vs. input voltage max15058 toc16 input voltage (v) rms input current (ma) 5.2 4.9 4.6 4.3 4.0 3.7 3.4 3.1 40 80 120 160 200 0 2.8 5.5 short circuit on output short-circuit hiccup mode max15058 toc15 i in 500ma/div v out 200mv/div i out 5a/div 200s /div shutdown current vs. input voltage max15058 toc14 input voltage (v) shutdown current (na) 5.2 4.7 4.2 3.7 3.2 10 20 30 40 50 60 70 80 90 100 0 2.7 v en = 0v soft-start waveforms (skip mode) (i out = 3a) max15058 toc13b v enable 5v/div v out 1v/div i lx 1a/div v pgood 5v/div 200s /div soft-start waveforms (pwm mode) (i out = 3a) max15058 toc13a v enable 5v/div v out 1v/div i lx 1a/div v pgood 5v/div 200s /div
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v in = 5v, v out = 1.8v, i load = 3a, circuit of figure 5, t a = +25 n c, unless otherwise noted.) starting into a prebiased output (i out = 2a) max15058 toc19 v enable 5v/div v out 1v/div v pgood 5v/div i lx 1a/div 200 s/div pwm mode starting into a prebiased output higher than set output max15058 toc21 v out 500mv/div v ss / refin 500mv/div i l 1a/div 400 s/div 1.8v 10i load at out starting into a prebiased output (no load) max15058 toc20b v enable 5v/div v out 1v/div v pgood 5v/div i lx 1a/div 200 s/div skip mode starting into a prebiased output (no load) max15058 toc20a v enable 5v/div v out 1v/div v pgood 5v/div i lx 1a/div 200 s/div pwm mode soft-start waveforms (external refin) (skip mode) max15058 toc18b v ss / refin 500mv/div v out 1v/div v pgood 5v/div i lx 1a/div 200 s/div no load soft-start waveforms (external refin) (pwm mode) max15058 toc18a v ss / refin 500mv/div v out 1v/div v pgood 5v/div i lx 1a/div 200 s/div no load
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 8 ______________________________________________________________________________________ typical operating characteristics (continued) (v in = 5v, v out = 1.8v, i load = 3a, circuit of figure 5, t a = +25 n c, unless otherwise noted.) input current (ma) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 input current in skip mode vs. output voltage max15058 toc23 output voltage (v) 1.2 1.7 2.2 2.7 3.2 no load v cc = 3.3v v cc = 5.0v case temperature vs. ambient temperature max15058 toc22 ambient temperature (c) case temperature (c) 60 40 20 0 -20 -20 0 20 40 60 80 100 -40 -40 80
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 _______________________________________________________________________________________ 9 pin description pin configuration bump name function a1 gnd analog ground/low-side switch source terminal. connect to the pcb copper plane at one point near the input bypass capacitor return terminal. a2 lx inductor connection. connect lx to the switched side of the inductor. lx is high impedance when the ic is in shutdown mode. a3 in input power supply. input supply range is from 2.7v to 5.5v. bypass with a minimum 10 f f ceramic capacitor to gnd. see figures 5 and 6. b1 comp voltage error-amplifier output. connect the necessary compensation network from comp to gnd. see the closing the loop: designing the compensation circuitry section. b2 skip skip-mode input. connect to en to select skip mode or leave unconnected for normal operation. b3 en enable input. en is a digital input that turns the regulator on and off. drive en high to turn on the regula - tor. connect to in for always-on operation. c1 fb feedback input. connect fb to the center tap of an external resistor-divider from the output to gnd to set the output voltage from 0.6v up to 94% of v in . c2 ss/refin soft-start/external voltage reference input. connect a capacitor from ss/refin to gnd to set the startup time. see the setting the soft-start time section for details on setting the soft-start time. apply a voltage reference from 0v to v in - 1.5v to drive soft-start externally. c3 pgood open-drain power-good output. pgood goes high when fb is above 555mv and pulls low if fb is below 527mv. wlp top view (bumps on bottom) ss/refin fb pgood skip comp en lx gnd in max15058 a1 b1 c1 c2 c3 b2 b3 a3 a2
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 10 _____________________________________________________________________________________ bias generator en logic, in uvlo thermal shdn skip-mode logic control logic skpm 0.58v ck gnd pgood en ss/refin fb ramp ck comp skip lx in shdn voltage reference oscillator ramp gen skpm lx skpm lx in in in sink source zx low-side source-sink current limit and zero- crossing comparator 0.6v high-side current limit strong prebiased forced start ss/refin buffer error amplifier 10a pwm comparator power-good comparator current-sense amplifier 0.555v rising, 0.527v falling max15058 c block diagram
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 ______________________________________________________________________________________ 11 detailed description the max15058 high-efficiency, current-mode switching regulator can deliver up to 3a of output current. the max15058 provides output voltages from 0.6v to 0.94 x v in from 2.7v to 5.5v input supplies, making the device ideal for on-board point-of-load applications. the max15058 delivers current-mode control archi - tecture using a high-gain transconductance error amplifier. the current-mode control architecture facilitates easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. the max15058 features a 1mhz fixed switching fre - quency, allowing for all-ceramic capacitor designs and fast transient responses. the high operating frequency minimizes the size of external components. the max15058 is available in a 1.5mm x 1.5mm (3 x 3 array) x 0.5mm pitch wlp package. the max15058 offers a selectable skip-mode functional - ity to reduce current consumption and achieve a higher efficiency at light output loads. the low r ds(on) integrat - ed switches (30m i high-side and 18m i low-side, typ) ensure high efficiency at heavy loads while minimizing critical inductances, making the layout design a much simpler task with respect to discrete solutions. utilizing a simple layout and footprint assures first-pass success in new designs. the max15058 features 1mhz q 15%, factory-trimmed, fixed-frequency pwm mode operation. the max15058 also offers capacitor-programmable, soft-start reducing inrush current, startup into prebias operation, and a pgood open-drain output for sequencing with other devices. controller functionpwm logic the controller logic block is the central processor that determines the duty cycle of the high-side mosfet under different line, load, and temperature conditions. under normal operation, where the current-limit and temperature protection are not triggered, the controller logic block takes the output from the pwm comparator and generates the driver signals for both high-side and low-side mosfets. the control logic block controls the break-before-make logic and all the necessary timing. the high-side mosfet turns on at the beginning of the oscillator cycle and turns off when the comp volt - age crosses the internal current-mode ramp waveform, which is the sum of the slope compensation ramp and the current-mode ramp derived from inductor current (current-sense block). the high-side mosfet also turns off if the maximum duty cycle is 94%, or when the current limit is reached. the low-side mosfet turns on for the remainder of the oscillation cycle. starting into a prebiased output the max15058 can soft-start into a prebiased output without discharging the output capacitor. in safe pre - biased startup, both low-side and high-side mosfets remain off to avoid discharging the prebiased output. pwm operation starts when the voltage on ss/refin crosses the voltage on fb. the max15058 can start into a prebiased voltage higher than the nominal set point without abruptly discharging the output. forced pwm operation starts when the ss/ refin voltage reaches 0.58v (typ), forcing the converter to start. in case of prebiased output, below or above the output nominal set point, if low-side sink current-limit threshold (set to the reduced value of -0.4a (typ) for the first 32 clock cycles and then set to -5a (typ)) is reached, the low-side switch turns off before the end of the clock period, and the high-side switch turns on until one of the following conditions is satisfied: ? high-side source current hits the reduced high-side current limit (0.4a, typ); in this case, the high-side switch is turned off for the remaining time of the clock period. ? the clock period ends. reduced high-side current limit is activated to recirculate the current into the high-side power switch rather than into the internal high-side body diode, which could be damaged. low-side sink current limit is provided to protect the low-side switch from excessive reverse current dur - ing prebiased operation. in skip mode operation, the prebias output needs to be lower than the set point. enable input the max15058 features independent device enable control and power-good signal that allow for flexible power sequencing. drive the enable input (en) high to enable the regulator, or connect en to in for always-on operation. power-good (pgood) is an open-drain out - put that asserts when v fb is above 555mv (typ), and deasserts low if v fb is below 527mv (typ). programmable soft-start (ss/refin) the max15058 utilizes a soft-start feature to slowly ramp up the regulated output voltage to reduce input inrush current during startup. connect a capacitor from ss/ refin to gnd to set the startup time (see the setting the soft-start time section for capacitor selection details).
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 12 _____________________________________________________________________________________ error amplifier a high-gain error am plifier provides accuracy for the voltage-feedback loop regulation. connect the neces - sary compensation network between comp and gnd (see the compensation design guidelines section). the error-amplifier transconductance is 1.5ms (typ). comp clamp low is set to 0.94v (typ), just below the slope ramp compensation valley, helping comp to rapidly return to the correct set point during load and line transients. pwm comparator the pwm comparator compares comp voltage to the current-derived ramp waveform (lx current to comp voltage transconductance value is 18a/v typ). to avoid instability due to subharmonic oscillations when the duty cycle is around 50% or higher, a slope compensation ramp is added to the current-derived ramp waveform. confirm the compensation ramp slope (0.3v x 1mhz = 0.3v/ f s) is equivalent to half the inductor current downslope in the worst case (load 3a, current ripple 30% and maximum duty-cycle operation of 94%). the slope compensation ramp valley is set to 1.15v (typ). overcurrent protection and hiccup when the converter output is shorted or the device is overloaded, each high-side mosfet current-limit event (5a typ) turns off the high-side mosfet and turns on the low-side mosfet. on each current-limit event a 3-bit counter is incremented. the counter is reset after three consecutive high-side mosfets turn on without reach - ing current limit. if the current-limit condition persists, the counter fills up reaching eight events. the control logic then discharges ss/refin, stops both high-side and low-side mosfets, and waits for a hiccup period (1024 clock cycles typ) before attempting a new soft- start sequence. the hiccup mode is also enabled during soft-start time. thermal-shutdown protection the max15058 contains an internal thermal sensor that limits the total power dissipation to protect the device in the event of an extended thermal fault condition. when the die temperature exceeds +150 n c (typ), the thermal sensor shuts down the device, turning off the dc-dc converter to allow the die to cool. after the die tempera - ture falls by 20 n c (typ), the device restarts, following the soft-start sequence. skip mode operation the max15058 operates in skip mode when skip is con - nected to en. when in skip mode, lx output becomes high impedance when the inductor current falls below 200ma (typ). the inductor current does not become negative. if during a clock cycle the inductor current falls below the 200ma threshold (during off-time), the low side turns off. at the next clock cycle, if the output voltage is above set point, the pwm logic keeps both high-side and low-side mosfets off. if instead the output voltage is below the set point, the pwm logic drives the high- side on for a minimum fixed on-time (300ns typ). in this way the system can skip cycles, reducing frequency of operations, and switches only as needed to service load at the cost of an increase in output voltage ripple (see the skip mode frequency and output ripple section). in skip mode, power dissipation is reduced and efficiency is improved at light loads because power mosfets do not switch at every clock cycle. applications information setting the output voltage the max15058 output voltage is adjustable from 0.6v up to 94% of v in by connecting fb to the center tap of a resistor-divider between the output and gnd (figure 1). choose r1 and r2 so that the dc errors due to the fb input bias current ( q 500na) do not affect the output volt - age accuracy. with lower value resistors, the dc error is reduced, but the amount of power consumed in the resistor-divider increases. a typical value for r2 is 10k i , but values between 5k i and 50k i are acceptable. once r2 is chosen, calculate r1 using: out fb v r1 = r2 1 v ? ? ? ? ? ? ? where the feedback threshold voltage, v fb = 0.6v (typ). when regulating for an output of 0.6v in skip mode, short fb to out and keep r2 connected from fb to gnd. inductor selection a high-valued inductor results in reduced inductor ripple current, leading to a reduced output ripple voltage. however, a high-valued inductor results in either a larger physical size or a high series resistance (dcr) and a lower saturation current rating. typically, choose an inductor value to produce a current ripple equal to 30% of load current. choose the inductor with the following formula: out out sw load in v v l 1 f lir i v ? ? = ? ? ? ? ? where f sw is the internally fixed 1mhz switching frequen - cy, and lir is the desired inductor current ratio (typically
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 ______________________________________________________________________________________ 13 set to 0.3). in addition, the peak inductor current, i l_pk , must always be below the minimum high-side current- limit value, i hscl , and the inductor saturation current rating, i l_sat . ensure that the following relationship is satisfied: ( ) l_pk load l hscl_, l_sat 1 i i i min i i 2 = + ? < input capacitor selection the input capacitor reduces the peak current drawn from the input power supply and reduces switching noise in the device. the total input capacitance must be equal to or greater than the value given by the following equation to keep the input ripple voltage within the specification and minimize the high-frequency ripple current being fed back to the input source: load out in sw in_ripple in i v c f v v = ? where d v in_ripple is the maximum-allowed input ripple voltage across the input capacitors and is recommend - ed to be less than 2% of the minimum input voltage, f sw is the switching frequency (1mhz), and i load is the output load. the impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. the input capacitor must meet the ripple current require - ment imposed by the switching currents. the rms input ripple current is given by: ( ) out in out ripple load in v v v i i v ? ? ? ? ? = ? ? ? ? where i ripple is the input rms ripple current. output capacitor selection the key selection parameters for the output capacitor are capacitance, esr, esl, and voltage rating. the parameters affect the overall stability, output ripple volt - age, and transient response of the dc-dc converter. the output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitors esr, and the voltage drop due to the figure 1. peak current-mode regulator transfer model l v comp i out comparator comp v comp v fb r c r out g mv v in power modulator output filter and load note: the g mod stage shown above models the average current of the inductor, i l , injected into the output load, i out , e.g., i l = i out . this can be used to simplify/model the modulation/control/power state circuitry shown within the boxed area. *note: c ff is optional and designed to extend th e regulator?s gain bandwidth and increased phase margin for some low-duty cycle applications. error amplifier feedback divider slope compensation ramp g mc dcr i l q ls v out v out q hs i out esr c out r load c c ref r out = 10 avea(db)/20 /g mv *c ff fb r1 r2 g mod pwm control logic c
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 14 _____________________________________________________________________________________ capacitors esl. estimate the output-voltage ripple due to the output capacitance, esr, and esl as follows: out out out esr_cout sw in sw out v v 1 v 1 r f l v 8 f c ? ? ? ? ? = ? + ? ? ? ? ? ? ? ? for ceramic capacitors, esr contribution is negligible: esr_out sw out 1 r 8 f c << for tantalum or electrolytic capacitors, esr contribution is dominant: esr_out sw out 1 r 8 f c >> use these equations f or initial output-capacitor selec - tion. determine final values by testing a prototype or an evaluation circuit. a smaller ripple current results in less output-voltage ripple. since the inductor ripple current is a factor of the inductor value, the output-voltage ripple decreases with larger inductance. use ceramic capaci - tors for low esr and low esl at the switching frequency of the converter. the ripple voltage due to esl is negli - gible when using ceramic capacitors. load-transient response also depends on the selected output capacitance. during a load transient, the output instantly changes by esr x d i load . before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. after a short time, the controller responds by regulating the output voltage back to the predetermined value. use higher c out values for applications that require light load operation or transition between heavy load and light load, triggering skip mode, causing output under - shooting or overshooting. when applying the load, limit the output undershoot by sizing c out according to the following formu la: load out co out i c 3f x v ? ? ? where d i load is the total load change, f co is the regula - tor unity-gain bandwidth (or zero crossover frequency), and d v out is the desired output undershooting. when removing the load and entering skip mode, the device cannot control output overshooting, since it has no sink current capability; see the skip mode frequency and output ripple section to properly size c out . skip mode frequency and output ripple in skip mode, the switching frequency (f skip ) and output ripple voltage (v out-ripple ) shown in figure 2 are cal - culated as follows: t on is a fixed time (300ns, typ); the peak inductor current reached is: in out skip limit on v v i t l ? ? = figure 2. skip mode waveform i l v out i skip-limit t on i load v out-ripple t off1 t off2 = n t ck
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 ______________________________________________________________________________________ 15 t off1 is the time needed for inductor current to reach the zero-current crossing limit (~0a): skip limit off1 out l i t v ? = during t on and t off1 , the output capacitor stores a charge equal to (see figure 2): ( ) 2 skip limit load in out out out 1 1 l x i i x v v v q 2 ? ? ? ? + ? ? ? ? ? ? = during t off2 (= n x t ck , number of clock cycles skipped), output capacitor loses this charge: ( ) out off2 load 2 skip limit load in out out off2 load q t i 1 1 l x i i x v v v t 2 xi ? ? = ? ? ? ? + ? ? ? ? ? = finally, frequency in skip mode is: skip on off1 off2 1 f t t t = + + output ripple in skip mode is: ( ) ( ) ( ) ( ) out ripple cout ripple esr ripple skip limit load on out esr,cout skip limit load skip limit out ripple esr,cout out in out skip limit load v v v i i x t c r x i i l x i v r c x v v x i i ? ? ? ? ? ? ? ? = + ? = + ? ? ? = + ? ? ? ? ? ? ? ? to limit output ripple in skip mode, size c out based on the above formula. all the above calculations are appli - cable only in skip mode. compensation design guidelines the max15058 uses a fixed -frequency, peak-current-mode control scheme to provide easy compensation and fast transient response. the inductor peak current is monitored on a cycle-by-cycle basis and compared to the comp voltage (output of the voltage error amplifier). the regula - tors duty cycle is modulated based on the inductors peak current value. this cycle-by-cycle control of the inductor current emulates a controlled current source. as a result, the induc tors pole frequency is shifted beyond the gain bandwidth of the regulator. system stability is provided with the addition of a simple series capacitor-resistor from comp to gnd. this pole-zero combination serves to tailor the desired response of the closed-loop system. the basic regulator loop consists of a power modulator (comprising the regulators pulse-width modulator, current sense and slope compensation ramps, control circuitry, mosfets, and inductor), the capacitive output filter and load, an output feedback divider, and a voltage-loop error amplifier with its associated compensation circuitry. see fig ure 1. the average current through the inductor is expressed as: l mod comp i g v = where i l is the average inductor current and g mod is the power modulators transconductance. for a buck converter: out load l v r i = where r load is the equivalent load resistor value. combining the above two relationships, the power mod - ulators transfer function in terms of v out with respect to v comp is: out load l load mod comp l mod v r i r g v i g = = the peak current-mode controllers modulator gain is attenuated by the equivalent divider ratio of the load resistance and the current-loop gains impedance. g mod becomes: ( ) ( ) mod mc load s sw 1 g dc g r 1 k 1 d 0.5 f l = ? ? ? ? + ? ? ? ? ? ? ? ? where r load = v out/iout(max) , f sw is the switching frequency, l is the output inductance, d is the duty cycle (v out /v in ), and k s is a slope compensation factor cal - culated from the following equation: ( ) slope slope sw mc s n in out s v f l g k 1 1 s v v = + = + ? where: slope slope slope sw sw v s v f t = = ( ) in out n mc v v s l g ? =
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 16 _____________________________________________________________________________________ as previously mentioned, the power modulators dominant pole is a function of the parallel effects of the load resis - tance and the current-loop gains equivalent impedance: ( ) pmod 1 s out load sw 1 f k 1 d 0.5 1 2 c esr r f l ? = ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? and knowing that the esr is typically much smaller than the parallel combination of the load and the current loop: ( ) 1 s load sw k 1 d 0.5 1 esr r f l ? ? ? ? ? ? ? ? ? ? ? << + ? ? ? ? ( ) pmod 1 s out load sw 1 f k 1 d 0.5 1 2 c r f l ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? which can be expressed as: ( ) s pmod out load sw out k 1 d 0.5 1 f 2 c r 2 f l c ? ? ? ? ? ? + note: depending on the applications specifics, the amplitude of the slope compensation ramp could have a significant impact on the modulators dominate pole. for low duty-cycle applications, it provides additional damping (phase lag) at/near the crossover frequency (see the closing the loop: designing the compensation circuitry section). there is no equivalent effect on the power modulator zero, f zmod . zmod zesr out 1 f f 2 c esr = = figure 3. asymptotic loop response of current-mode regulator gain 1st asymptote r2 (r1 + r2) -1 10 avea(db)/20 g mc r load {1 + r load [k s (1 - d) - 0.5] (l f sw ) -1 } -1 2nd asymptote r2 (r1 + r2) -1 g mv (2gc c ) -1 g mc r load {1 + r load [k s (1 - d) - 0.5] (l f sw ) -1 } -1 3rd asymptote r2 (r1 + r2) -1 g mv (2gc c ) -1 g mc r load {1 + r load [k s (1 - d) - 0.5] (l f sw ) -1 } -1 (2gc out {r load -1 + [k s (1 - d) - 0.5] (l f sw ) -1 } -1 ) -1 4th asymptote r2 (r1 + r2) -1 g mv r c g mc r load {1 + r load [k s (1 - d) - 0.5] (l f sw ) -1 } -1 (2gc out {r load -1 + [k s (1 - d) - 0.5] (l f sw ) -1 } -1 ) -1 5th asymptote r2 (r1 + r2) -1 g mv r c g mc r load {1 + r load [k s (1 - d) - 0.5] (l f sw ) -1 } -1 (2gc out {r load -1 + [k s (1 - d) - 0.5] (l f sw ) -1 } -1 ) -1 (0.5 f sw ) 2 (2gf) -2 6th asymptote r2 (r1 + r2) -1 g mv r c g mc r load {1 + r load [k s (1 - d) - 0.5] (l f sw ) -1 } -1 esr {r load -1 + [k s (1 - d) - 0.5] (l f sw ) -1 } -1 (0.5 f sw ) 2 (2gf) -2 unity 1st pole [2gc c (10 avea(db)/20 - g mv -1 )] -1 2nd pole f pmod * 3rd pole (dbl) 0.5 f sw 2nd zero (2gc out esr) -1 frequency f co 1st zero (2gc c r c ) -1 note: r out = 10 avea(db)/20 g mv -1 f pmod = [2gc out (esr + {r load -1 + [k s (1 - d) - 0.5] (l f sw ) -1 } -1 )] -1 which for esr << {r load -1 + [k s (1 - d) - 0.5] (l f sw ) -1 } -1 becomes f pmod = [2gc out {r load -1 + [k s (1 - d) - 0.5] (l f sw ) -1 } -1 ] -1 f pmod = (2gc out r load ) -1 + [k s (1 - d) - 0.5] (2gc out l f sw ) -1
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 ______________________________________________________________________________________ 17 the effect of the inner current loop at higher frequen - cies is modeled as a double-pole (complex conjugate) frequency term, g sampling (s), as shown: ( ) ( ) sampling 2 2 sw c sw 1 g s s s 1 f q f = + + where the sampling effect quality factor, q c , is: ( ) c s 1 q k 1 d 0.5 = ? ? ? ? ? ? and the resonant frequency is: sampling (s) = f sw or: sw sampling f f 2 = having defined the power modulators transfer function, the total system transfer can be written as follows (see figure 3): gain(s) = g ff (s) g ea (s) g mod (dc) g filter (s) g sampling (s) where: ( ) ( ) ( ) ff ff ff sc r1 1 r2 g s r1 r2 sc r1|| r2 1 + = + ? ? + ? ? leaving c ff empty, g ff(s) becomes: ( ) ff r2 g s r1 r2 = + also: ( ) ( ) c c avea(db)/20 ea avea(db)/20 c c mv sc r 1 g s 10 10 sc r 1 g + = ? ? ? ? ? ? ? + ? + ? ? ? ? ? ? ? ? which simplifies to: ( ) ( ) c c avea(db)/20 ea avea(db)/20 c mv sc r 1 g s 10 10 sc 1 g + = ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? avea(db)/20 c mv 10 when r g << ( ) ( ) ( ) out filter load 1 s out load sw sc esr 1 g s r k 1 d 0.5 1 sc 1 r f l ? + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? the dominant poles and zeros of the transfer loop gain are shown below: ( ) ( ) mv p1 avea(db)/20 c p2 s 1 out load sw p3 sw z1 c c z2 out g f 2 10 c 1 f k 1 d 0.5 1 2 c r f l 1 f f 2 1 f 2 c r 1 f 2 c esr ? = = ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = = = the order of pole-zero occurrence is: p1 p2 z1 co p3 z2 f f f f f f < < < under heavy load, f p2 , approaches f z1 . figure 3 shows a graphical representation of the asymptotic system closed-loop response, including dominant pole and zero locations. the loop responses fourth asymptote (in bold, figure 3) is the one of interest in establishing the desired cross - over frequency (and determining the compensation component values). a lower crossover frequency pro - vides for stable closed-loop operation at the expense of a slower load- and line-transient response. increasing the crossover frequency improves the transient response at the (potential) cost of system instability. a standard rule of thumb sets the crossover frequency between 1/10 and 1/5 of the switching frequency. first, select the passive power and decoupling components that meet the applications requirements. then, choose the small-signal compensation components to achieve the desired clo sed-loop frequency response and phase margin as outlined in the closing the loop: designing the compensation circuitry section . closing the loop: designing the compensation circuitry 1) select the desired crossover frequency. choose f co approximately 1/10 to 1/5 of the switching frequency (f sw ). 2) determine r c by setting the system transfers fourth asymptote gain equal to unity (assuming f co > f z1 , f p2 , and f p1 ) where:
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 18 _____________________________________________________________________________________ ( ) ( ) load s sw c co out mv mc load s load sw r k 1 d 0.5 1 l f r1 r2 r 2 f c r2 g g r 1 esr k 1 d 0.5 1 r l f ? ? ? ? ? ? ? ? + ? ? ? ? + ? ? = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? and where the esr is much smaller than the parallel combination of the equivalent load resistance and the current loop impedance, e.g.,: ( ) s load sw 1 esr k 1 d 0.5 1 r l f << ? ? ? ? ? ? ? ? + ? ? ? ? ? ? r c becomes: co out c mv mc 2 f c r1 r2 r r2 g g + = 3) determine c c by selecting the desired first sys - tem zero, f z1 , based on the desired phase margin. typically, setting f z1 below 1/5 of f co provides suf - ficient phase margin. co z1 c c f 1 f 2 c r 5 = therefore: c co c 5 c 2 f r 4) for low duty-cycle applications, the addition of a phase-leading capacitor (c ff in figure 1) helps mitigate the phase lag of the damped half-frequency double pole. adding a second zero near to but below the desired crossover frequency increases both the closed-loop phase margin and the regulators unity- gain bandwidth (crossover frequency). select the capacitor as follows: ( ) ff co 1 c 2 f r1|| r2 = this guarantees the additional phase-leading zero occurs at a frequency lower than f co from: phase_lead ff 1 f 2 c r1 = using c ff the zero-pole order is adjusted as follows: p1 p2 z1 ff ff co p3 z2 1 1 f f f 2 c r1 2 c (r1|| r2) f f f < < < < < confirm the desired operation of c ff empirically. the phase lead of c ff diminishes as the output voltage is a smaller multiple of the reference voltage, e.g., below about 1v. do not use c ff when v out = v fb . setting the soft-start time the soft-start feature ramps up the output voltage slowly, reducing input inrush current during startup. size the c ss capacitor to achieve the desired soft-start time, t ss, using: ss ss ss fb i t c v = i ss , the soft-start current, is 10 f a (typ) and v fb , the output feedback voltage threshold, is 0.6v (typ). when using large c out capacitance values, the high-side current limit can trigger during the soft-start period. to ensure the correct soft-start time, t ss , choose c ss large enough to satisfy: out ss ss out hscl_ out fb v i c c (i i ) v >> ? i hscl_ is the typical high-side mosfet current-limit value. an exte rnal tracking reference with steady-state value between 0v and v in - 1.8v can be applied to ss/refin. in this case, connect an rc network from external track - ing reference and ss/refin, as shown in figure 4. the recomm ended value for r ss is a pproximately 1k i . r ss is needed to ensure that, during hiccup period, ss/ refin can be internally pulled down. when an external reference is connected to ss/refin, the soft-start must be provided externally. figure 4. rc network for external reference at ss/refin c ss r ss v ref_ext ss/refin max15058
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 ______________________________________________________________________________________ 19 power dissipation the max15058 is available in a 9-bump wlp package and can dissipate up to 1127mw at t a = +70 n c. when the die temperature exceeds +150 n c, the thermal-shut - down protection is activated (see the thermal-shutdown protection section). layout procedure careful pcb layout is critical to achieve clean and stable operation. it is highly recommended to duplicate the max15058 evaluation kit layout for optimum perfor - mance. if deviation is necessary, follow these guidelines for good pcb layout: 1) connect the signal and ground planes at a single point immediately adjacent to the gnd bump of the ic. 2) place capacitors on in and ss/refin as close as possible to the ic and the corresponding pad using direct traces. 3) keep the high-current paths as short and wide as possible. keep the path of switching current short and minimize the loop area formed by lx, the output capacitors, and the input capacitors. 4) connect in, lx, and gnd separately to a large cop - per area to help cool the ic to further improve effi - ciency. 5) ensure all feedback connections are short and direct. place the feedback resistors and compensa - tion components as close as possible to the ic. 6) route high-speed switching nodes (such as lx) away from sensitive analog areas (such as fb and comp). figure 5. application circuit for pwm mode operation lx gnd fb comp c out 22f x 2 output 1.8v at 3a r 2 4.02ki r 1 8.06ki r c 5.36ki c c 1nf l out 1h c ff 100pf 1.2i 1nf r pull 20ki c in 22f in pgood en enable skip on off c ss 22nf ss/refin max15058 input 2.8v to 5.5v (ice in06142)
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 20 _____________________________________________________________________________________ package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos figure 6. application circuit for skip mode operation lx gnd fb comp c out 22f x 2 output 1.8v at 3a r 2 4.02ki r 1 8.06ki r c 5.36ki c c 1nf l out 1h c ff 100pf 1.2i 1nf r pull 20ki c in 22f in pgood en enable skip on off c ss 22nf ss/refin max15058 input 2.8v to 5.5v (ice in06142) package type package code outline no. land pattern no. 9 wlp w91e1z+1 21-0508 refer to application note 1891
high-efficiency, 3a, current-mode synchronous, step-down switching regulator max15058 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 21 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 12/10 initial release 1 3/11 revised package information section. 20 2 7/11 changed the 1.65mm x 1.65mm, 9-bump package information to 1.5mm x 1.5mm, 9-bump package information. inserted typical operating circuit on page one. 1, 11

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